powerpc-wrs-vxworks

Arch powerpc
Family vxworks
OS vxworks

CFGs:

  • debug_assertions
  • panic="unwind"
  • target_abi=""
  • target_arch="powerpc"
  • target_endian="big"
  • target_env="gnu"
  • target_family="unix"
  • target_feature="crt-static"
  • target_feature="llvm14-builtins-abi"
  • target_has_atomic="16"
  • target_has_atomic="32"
  • target_has_atomic="8"
  • target_has_atomic="ptr"
  • target_has_atomic_equal_alignment="16"
  • target_has_atomic_equal_alignment="32"
  • target_has_atomic_equal_alignment="8"
  • target_has_atomic_equal_alignment="ptr"
  • target_has_atomic_load_store="16"
  • target_has_atomic_load_store="32"
  • target_has_atomic_load_store="8"
  • target_has_atomic_load_store="ptr"
  • target_os="vxworks"
  • target_pointer_width="32"
  • target_thread_local
  • target_vendor="wrs"
  • unix

CPUs

Feature Name Feature Explanation LLVM
altivec Enable Altivec instructions. ⛔️
power8-altivec Enable POWER8 Altivec instructions. ⛔️
power9-altivec Enable POWER9 Altivec instructions. ⛔️
power8-vector Enable POWER8 vector instructions. ⛔️
power9-vector Enable POWER9 vector instructions. ⛔️
vsx Enable VSX instructions. ⛔️
crt-static Enables C Run-time Libraries to be statically linked. ⛔️
64bit Enable 64-bit instructions. ✅
64bitregs Enable 64-bit registers usage for ppc32 [beta]. ✅
aix AIX OS. ✅
allow-unaligned-fp-access CPU does not trap on unaligned FP access. ✅
booke Enable Book E instructions. ✅
bpermd Enable the bpermd instruction. ✅
cmpb Enable the cmpb instruction. ✅
crbits Use condition-register bits individually. ✅
crypto Enable POWER8 Crypto instructions. ✅
direct-move Enable Power8 direct move instructions. ✅
e500 Enable E500/E500mc instructions. ✅
efpu2 Enable Embedded Floating-Point APU 2 instructions. ✅
extdiv Enable extended divide instructions. ✅
fcpsgn Enable the fcpsgn instruction. ✅
float128 Enable the __float128 data type for IEEE-754R Binary128.. ✅
fpcvt Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions. ✅
fprnd Enable the fri[mnpz] instructions. ✅
fpu Enable classic FPU instructions. ✅
fre Enable the fre instruction. ✅
fres Enable the fres instruction. ✅
frsqrte Enable the frsqrte instruction. ✅
frsqrtes Enable the frsqrtes instruction. ✅
fsqrt Enable the fsqrt instruction. ✅
fuse-add-logical Target supports Add with Logical Operations fusion. ✅
fuse-addi-load Power8 Addi-Load fusion. ✅
fuse-addis-load Power8 Addis-Load fusion. ✅
fuse-arith-add Target supports Arithmetic Operations with Add fusion. ✅
fuse-back2back Target supports general back to back fusion. ✅
fuse-cmp Target supports Comparison Operations fusion. ✅
fuse-logical Target supports Logical Operations fusion. ✅
fuse-logical-add Target supports Logical with Add Operations fusion. ✅
fuse-sha3 Target supports SHA3 assist fusion. ✅
fuse-store Target supports store clustering. ✅
fuse-wideimm Target supports Wide-Immediate fusion. ✅
fuse-zeromove Target supports move to SPR with branch fusion. ✅
fusion Target supports instruction fusion. ✅
hard-float Enable floating-point instructions. ✅
htm Enable Hardware Transactional Memory instructions. ✅
icbt Enable icbt instruction. ✅
invariant-function-descriptors Assume function descriptors are invariant. ✅
isa-future-instructions Enable instructions for Future ISA.. ✅
isa-v206-instructions Enable instructions in ISA 2.06.. ✅
isa-v207-instructions Enable instructions in ISA 2.07.. ✅
isa-v30-instructions Enable instructions in ISA 3.0.. ✅
isa-v31-instructions Enable instructions in ISA 3.1.. ✅
isel Enable the isel instruction. ✅
ldbrx Enable the ldbrx instruction. ✅
lfiwax Enable the lfiwax instruction. ✅
longcall Always use indirect calls. ✅
mfocrf Enable the MFOCRF instruction. ✅
mma Enable MMA instructions. ✅
modern-aix-as AIX system assembler is modern enough to support new mnes. ✅
msync Has only the msync instruction instead of sync. ✅
paired-vector-memops 32Byte load and store instructions. ✅
partword-atomics Enable l[bh]arx and st[bh]cx.. ✅
pcrelative-memops Enable PC relative Memory Ops. ✅
popcntd Enable the popcnt[dw] instructions. ✅
power10-vector Enable POWER10 vector instructions. ✅
ppc-postra-sched Use PowerPC post-RA scheduling strategy. ✅
ppc-prera-sched Use PowerPC pre-RA scheduling strategy. ✅
ppc4xx Enable PPC 4xx instructions. ✅
ppc6xx Enable PPC 6xx instructions. ✅
predictable-select-expensive Prefer likely predicted branches over selects. ✅
prefix-instrs Enable prefixed instructions. ✅
privileged Add privileged instructions. ✅
quadword-atomics Enable lqarx and stqcx.. ✅
recipprec Assume higher precision reciprocal estimates. ✅
rop-protect Add ROP protect. ✅
secure-plt Enable secure plt mode. ✅
slow-popcntd Has slow popcnt[dw] instructions. ✅
spe Enable SPE instructions. ✅
stfiwx Enable the stfiwx instruction. ✅
two-const-nr Requires two constant Newton-Raphson computation. ✅
vectors-use-two-units Vectors use two units. ✅