armebv7r-none-eabihf

Arch arm
Family none
OS none

CFGs:

  • debug_assertions
  • panic="abort"
  • target_abi="eabihf"
  • target_arch="arm"
  • target_endian="big"
  • target_env=""
  • target_feature="dsp"
  • target_feature="llvm14-builtins-abi"
  • target_feature="rclass"
  • target_feature="thumb2"
  • target_feature="v5te"
  • target_feature="v6"
  • target_feature="v6k"
  • target_feature="v6t2"
  • target_feature="v7"
  • target_feature="vfp2"
  • target_has_atomic="16"
  • target_has_atomic="32"
  • target_has_atomic="8"
  • target_has_atomic="ptr"
  • target_has_atomic_equal_alignment="16"
  • target_has_atomic_equal_alignment="32"
  • target_has_atomic_equal_alignment="8"
  • target_has_atomic_equal_alignment="ptr"
  • target_has_atomic_load_store="16"
  • target_has_atomic_load_store="32"
  • target_has_atomic_load_store="8"
  • target_has_atomic_load_store="ptr"
  • target_os="none"
  • target_pointer_width="32"
  • target_vendor="unknown"

CPUs

Feature Name Feature Explanation LLVM
aclass Is application profile ('A' series). ⛔️
mclass Is microcontroller profile ('M' series). ⛔️
rclass Is realtime profile ('R' series). ⛔️
dsp Supports DSP instructions in ARM and/or Thumb2. ⛔️
neon Enable NEON instructions. ⛔️
crc Enable support for CRC instructions. ⛔️
crypto Enable support for Cryptography extensions. ⛔️
aes Enable AES support. ⛔️
sha2 Enable SHA1 and SHA256 support. ⛔️
i8mm Enable Matrix Multiply Int8 Extension. ⛔️
dotprod Enable support for dot product instructions. ⛔️
v5te Support ARM v5TE, v5TEj, and v5TExp instructions. ⛔️
v6 Support ARM v6 instructions. ⛔️
v6k Support ARM v6k instructions. ⛔️
v6t2 Support ARM v6t2 instructions. ⛔️
v7 Support ARM v7 instructions. ⛔️
v8 Support ARM v8 instructions. ⛔️
vfp2 Enable VFP2 instructions. ⛔️
vfp3 Enable VFP3 instructions. ⛔️
vfp4 Enable VFP4 instructions. ⛔️
fp-armv8 Enable ARMv8 FP. ⛔️
thumb-mode Thumb mode. ⛔️
thumb2 Enable Thumb2 instructions. ⛔️
d32 Extend FP to 32 double registers. ⛔️
crt-static Enables C Run-time Libraries to be statically linked. ⛔️
32bit Prefer 32-bit Thumb instrs. ✅
8msecext Enable support for ARMv8-M Security Extensions. ✅
a12 Cortex-A12 ARM processors. ✅
a15 Cortex-A15 ARM processors. ✅
a17 Cortex-A17 ARM processors. ✅
a32 Cortex-A32 ARM processors. ✅
a35 Cortex-A35 ARM processors. ✅
a5 Cortex-A5 ARM processors. ✅
a53 Cortex-A53 ARM processors. ✅
a55 Cortex-A55 ARM processors. ✅
a57 Cortex-A57 ARM processors. ✅
a7 Cortex-A7 ARM processors. ✅
a72 Cortex-A72 ARM processors. ✅
a73 Cortex-A73 ARM processors. ✅
a75 Cortex-A75 ARM processors. ✅
a76 Cortex-A76 ARM processors. ✅
a77 Cortex-A77 ARM processors. ✅
a78c Cortex-A78C ARM processors. ✅
a8 Cortex-A8 ARM processors. ✅
a9 Cortex-A9 ARM processors. ✅
aapcs-frame-chain Create an AAPCS compliant frame chain. ✅
aapcs-frame-chain-leaf Create an AAPCS compliant frame chain for leaf functions. ✅
acquire-release Has v8 acquire/release (lda/ldaex etc) instructions. ✅
armv2 ARMv2 architecture. ✅
armv2a ARMv2a architecture. ✅
armv3 ARMv3 architecture. ✅
armv3m ARMv3m architecture. ✅
armv4 ARMv4 architecture. ✅
armv4t ARMv4t architecture. ✅
armv5t ARMv5t architecture. ✅
armv5te ARMv5te architecture. ✅
armv5tej ARMv5tej architecture. ✅
armv6 ARMv6 architecture. ✅
armv6-m ARMv6m architecture. ✅
armv6j ARMv7a architecture. ✅
armv6k ARMv6k architecture. ✅
armv6kz ARMv6kz architecture. ✅
armv6s-m ARMv6sm architecture. ✅
armv6t2 ARMv6t2 architecture. ✅
armv7-a ARMv7a architecture. ✅
armv7-m ARMv7m architecture. ✅
armv7-r ARMv7r architecture. ✅
armv7e-m ARMv7em architecture. ✅
armv7k ARMv7a architecture. ✅
armv7s ARMv7a architecture. ✅
armv7ve ARMv7ve architecture. ✅
armv8-a ARMv8a architecture. ✅
armv8-m.base ARMv8mBaseline architecture. ✅
armv8-m.main ARMv8mMainline architecture. ✅
armv8-r ARMv8r architecture. ✅
armv8.1-a ARMv81a architecture. ✅
armv8.1-m.main ARMv81mMainline architecture. ✅
armv8.2-a ARMv82a architecture. ✅
armv8.3-a ARMv83a architecture. ✅
armv8.4-a ARMv84a architecture. ✅
armv8.5-a ARMv85a architecture. ✅
armv8.6-a ARMv86a architecture. ✅
armv8.7-a ARMv87a architecture. ✅
armv8.8-a ARMv88a architecture. ✅
armv9-a ARMv9a architecture. ✅
armv9.1-a ARMv91a architecture. ✅
armv9.2-a ARMv92a architecture. ✅
armv9.3-a ARMv93a architecture. ✅
atomics-32 Assume that lock-free 32-bit atomics are available. ✅
avoid-movs-shop Avoid movs instructions with shifter operand. ✅
avoid-partial-cpsr Avoid CPSR partial update for OOO execution. ✅
bf16 Enable support for BFloat16 instructions. ✅
cde Support CDE instructions. ✅
cdecp0 Coprocessor 0 ISA is CDEv1. ✅
cdecp1 Coprocessor 1 ISA is CDEv1. ✅
cdecp2 Coprocessor 2 ISA is CDEv1. ✅
cdecp3 Coprocessor 3 ISA is CDEv1. ✅
cdecp4 Coprocessor 4 ISA is CDEv1. ✅
cdecp5 Coprocessor 5 ISA is CDEv1. ✅
cdecp6 Coprocessor 6 ISA is CDEv1. ✅
cdecp7 Coprocessor 7 ISA is CDEv1. ✅
cheap-predicable-cpsr Disable +1 predication cost for instructions updating CPSR. ✅
cortex-a710 Cortex-A710 ARM processors. ✅
cortex-a78 Cortex-A78 ARM processors. ✅
cortex-x1 Cortex-X1 ARM processors. ✅
cortex-x1c Cortex-X1C ARM processors. ✅
db Has data barrier (dmb/dsb) instructions. ✅
dfb Has full data barrier (dfb) instruction. ✅
disable-postra-scheduler Don't schedule again after register allocation. ✅
dont-widen-vmovs Don't widen VMOVS to VMOVD. ✅
execute-only Enable the generation of execute only code.. ✅
expand-fp-mlx Expand VFP/NEON MLA/MLS instructions. ✅
exynos Samsung Exynos processors. ✅
fix-cmse-cve-2021-35465 Mitigate against the cve-2021-35465 security vulnurability. ✅
fix-cortex-a57-aes-1742098 Work around Cortex-A57 Erratum 1742098 / Cortex-A72 Erratum 1655431 (AES). ✅
fp-armv8d16 Enable ARMv8 FP with only 16 d-registers. ✅
fp-armv8d16sp Enable ARMv8 FP with only 16 d-registers and no double precision. ✅
fp-armv8sp Enable ARMv8 FP with no double precision. ✅
fp16 Enable half-precision floating point. ✅
fp16fml Enable full half-precision floating point fml instructions. ✅
fp64 Floating point unit supports double precision. ✅
fpao Enable fast computation of positive address offsets. ✅
fpregs Enable FP registers. ✅
fpregs16 Enable 16-bit FP registers. ✅
fpregs64 Enable 64-bit FP registers. ✅
fullfp16 Enable full half-precision floating point. ✅
fuse-aes CPU fuses AES crypto operations. ✅
fuse-literals CPU fuses literal generation operations. ✅
harden-sls-blr Harden against straight line speculation across indirect calls. ✅
harden-sls-nocomdat Generate thunk code for SLS mitigation in the normal text section. ✅
harden-sls-retbr Harden against straight line speculation across RETurn and BranchRegister instructions. ✅
hwdiv Enable divide instructions in Thumb. ✅
hwdiv-arm Enable divide instructions in ARM mode. ✅
iwmmxt ARMv5te architecture. ✅
iwmmxt2 ARMv5te architecture. ✅
krait Qualcomm Krait processors. ✅
kryo Qualcomm Kryo processors. ✅
lob Enable Low Overhead Branch extensions. ✅
long-calls Generate calls via indirect call instructions. ✅
loop-align Prefer 32-bit alignment for loops. ✅
m3 Cortex-M3 ARM processors. ✅
m7 Cortex-M7 ARM processors. ✅
mp Supports Multiprocessing extension. ✅
muxed-units Has muxed AGU and NEON/FPU. ✅
mve Support M-Class Vector Extension with integer ops. ✅
mve.fp Support M-Class Vector Extension with integer and floating ops. ✅
mve1beat Model MVE instructions as a 1 beat per tick architecture. ✅
mve2beat Model MVE instructions as a 2 beats per tick architecture. ✅
mve4beat Model MVE instructions as a 4 beats per tick architecture. ✅
nacl-trap NaCl trap. ✅
neon-fpmovs Convert VMOVSR, VMOVRS, VMOVS to NEON. ✅
neonfp Use NEON for single precision FP. ✅
neoverse-v1 Neoverse-V1 ARM processors. ✅
no-branch-predictor Has no branch predictor. ✅
no-bti-at-return-twice Don't place a BTI instruction after a return-twice. ✅
no-movt Don't use movt/movw pairs for 32-bit imms. ✅
no-neg-immediates Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.. ✅
noarm Does not support ARM mode execution. ✅
nonpipelined-vfp VFP instructions are not pipelined. ✅
pacbti Enable Pointer Authentication and Branch Target Identification. ✅
perfmon Enable support for Performance Monitor extensions. ✅
prefer-ishst Prefer ISHST barriers. ✅
prefer-vmovsr Prefer VMOVSR. ✅
prof-unpr Is profitable to unpredicate. ✅
r4 Cortex-R4 ARM processors. ✅
r5 Cortex-R5 ARM processors. ✅
r52 Cortex-R52 ARM processors. ✅
r7 Cortex-R7 ARM processors. ✅
ras Enable Reliability, Availability and Serviceability extensions. ✅
read-tp-hard Reading thread pointer from register. ✅
reserve-r9 Reserve R9, making it unavailable as GPR. ✅
ret-addr-stack Has return address stack. ✅
sb Enable v8.5a Speculation Barrier. ✅
slow-fp-brcc FP compare + branch is slow. ✅
slow-load-D-subreg Loading into D subregs is slow. ✅
slow-odd-reg VLDM/VSTM starting with an odd register is slow. ✅
slow-vdup32 Has slow VDUP32 ✅
slow-vgetlni32 Has slow VGETLNi32 ✅
slowfpvfmx Disable VFP / NEON FMA instructions. ✅
slowfpvmlx Disable VFP / NEON MAC instructions. ✅
soft-float Use software floating point features.. ✅
splat-vfp-neon Splat register from VFP to NEON. ✅
strict-align Disallow all unaligned memory access. ✅
swift Swift ARM processors. ✅
trustzone Enable support for TrustZone security extensions. ✅
use-mipipeliner Use the MachinePipeliner. ✅
use-misched Use the MachineScheduler. ✅
v4t Support ARM v4T instructions. ✅
v5t Support ARM v5T instructions. ✅
v6m Support ARM v6M instructions. ✅
v7clrex Has v7 clrex instruction. ✅
v8.1a Support ARM v8.1a instructions. ✅
v8.1m.main Support ARM v8-1M Mainline instructions. ✅
v8.2a Support ARM v8.2a instructions. ✅
v8.3a Support ARM v8.3a instructions. ✅
v8.4a Support ARM v8.4a instructions. ✅
v8.5a Support ARM v8.5a instructions. ✅
v8.6a Support ARM v8.6a instructions. ✅
v8.7a Support ARM v8.7a instructions. ✅
v8.8a Support ARM v8.8a instructions. ✅
v8m Support ARM v8M Baseline instructions. ✅
v8m.main Support ARM v8M Mainline instructions. ✅
v9.1a Support ARM v9.1a instructions. ✅
v9.2a Support ARM v9.2a instructions. ✅
v9.3a Support ARM v9.3a instructions. ✅
v9a Support ARM v9a instructions. ✅
vfp2sp Enable VFP2 instructions with no double precision. ✅
vfp3d16 Enable VFP3 instructions with only 16 d-registers. ✅
vfp3d16sp Enable VFP3 instructions with only 16 d-registers and no double precision. ✅
vfp3sp Enable VFP3 instructions with no double precision. ✅
vfp4d16 Enable VFP4 instructions with only 16 d-registers. ✅
vfp4d16sp Enable VFP4 instructions with only 16 d-registers and no double precision. ✅
vfp4sp Enable VFP4 instructions with no double precision. ✅
virtualization Supports Virtualization extension. ✅
vldn-align Check for VLDn unaligned access. ✅
vmlx-forwarding Has multiplier accumulator forwarding. ✅
vmlx-hazards Has VMLx hazards. ✅
wide-stride-vfp Use a wide stride when allocating VFP registers. ✅
xscale ARMv5te architecture. ✅
zcz Has zero-cycle zeroing instructions. ✅